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(R)
M
VNQ810M
QUAD CHANNEL HIGH SIDE DRIVER
TYPE VNQ810M (*) Per each channel
RDS(on) 150 m (*)
IOUT 0.6 A (*)
VCC 36 V
CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS s ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s PROTECTION AGAINST LOSS OF GROUND s VERY LOW STAND-BY CURRENT s REVERSE BATTERY PROTECTION (**)
s s
SO-28 (DOUBLE ISLAND) ORDER CODES
PACKAGE
SO-28
TUBE VNQ810M
T&R VNQ810M13TR
DESCRIPTION The VNQ810M is a quad HSD formed by assembling two VND810M chips in the same SO28 package.The VND810M is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device ABSOLUTE MAXIMUM RATING
Symbol VCC - VCC - Ignd IOUT - IOUT IIN ISTAT
against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The current limitation threshold is aimed at detecting the 21W/12V standard bulb as an overload fault. The device detects open load condition both in on and off state . Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.
Value 41 -0.3 -200 Internally Limited -6 +/- 10 +/- 10 4000 4000 5000 5000 174 6.25 Internally Limited -55 to 150 Unit V V mA A A mA mA V V V V mJ W C C
Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - STATUS - OUTPUT - VCC Maximum Switching Energy (L=310mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=0.9A) Power dissipation (per island) at Tlead=25C Junction Operating Temperature Storage Temperature
VESD
EMAX Ptot Tj Tstg
(**) See application schematic at page 9
January 2003
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VNQ810M
BLOCK DIAGRAM
VCC1,2
Vcc CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND1,2
CLAMP 1 OUTPUT1 DRIVER 1 CLAMP 2
INPUT1
STATUS1 CURRENT LIMITER 1 LOGIC OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 STATUS2 OPENLOAD ON 2 DRIVER 2 OUTPUT2
OPENLOAD OFF 2 OVERTEMP. 2 VCC3,4 Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE GND3,4 INPUT3 CLAMP 3 OUTPUT3 DRIVER 3 CLAMP 4 STATUS3 CURRENT LIMITER 3 LOGIC OVERTEMP. 3 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 OPENLOAD ON 4 DRIVER 4 OUTPUT4
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VNQ810M
CURRENT AND VOLTAGE CONVENTIONS
IS1,2
IS3,4 VCC1,2 IIN1 VIN1 VSTAT1 VIN2 VSTAT2 VIN3 VSTAT3 ISTAT1 IIN2 ISTAT2 IIN3 ISTAT3 IIN4 INPUT1 STATUS1 INPUT2 STATUS2 INPUT3 STATUS3 INPUT4 STATUS4 GND1,2 IGND1,2 GND3,4 IGND3,4 OUTPUT4 OUTPUT2 IOUT3 OUTPUT3 IOUT4 VOUT4 VOUT3 OUTPUT1 IOUT2 VOUT1 VOUT2 IOUT1 VCC3,4 VCC3,4
VCC1,2
VIN4 ISTAT4 VSTAT4
CONNECTION DIAGRAM (TOP VIEW)
VCC1,2 GND 1,2 INPUT1 STATUS1 STATUS2 INPUT2 VCC1,2 VCC3,4 GND 3,4 INPUT3 STATUS3 STATUS4 INPUT4 VCC3,4
1
28
VCC1,2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4
14
15
VCC3,4
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VNQ810M
THERMAL DATA (Per island)
Symbol Rthj-lead Rthj-amb Rthj-amb Parameter Thermal Resistance Junction-lead per chip Thermal Resistance Junction-ambient (one chip ON) Thermal Resistance Junction-ambient (two chips ON) Value 20 60 (*) 46 (*) Unit C/W C/W C/W
(*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8VSymbol VCC (**) VUSD (**) VOV (**) RON Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance Test Conditions Min 5.5 3 36 Typ 13 4 Max 36 5.5 150 12 12 5 0 -75 300 40 25 7 50 0 5 3 Unit V V V m m A A mA A A A A
IOUT=0.5A; Tj=25C IOUT=0.5A; VCC> 8V Off State; VCC=13V; VIN=VOUT=0V
IS (**)
Supply Current
Off State; VCC=13V; VIN=VOUT=0V; Tj =25C On State; VCC=13V; VIN=5V; IOUT=0A
IL(off1) IL(off2) IL(off3) IL(off4)
Off State Output Current Off State Output Current Off State Output Current Off State Output Current
VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; Vcc=13V; Tj =125C VIN=VOUT=0V; Vcc=13V; Tj =25C
SWITCHING (Per each Channel) (VCC=13V)
Symbol td(on) td(off) Parameter Turn-on Delay Time Turn-off Delay Time Test Conditions RL=26 from VIN rising edge to VOUT=1.3V RL=26 from VIN falling edge to VOUT=11.7V RL=26 from VOUT=1.3V to VOUT=10.4V Min Typ 30 30 See relative diagram See relative diagram Max Unit s s V/s
dVOUT/dt(on) Turn-on Voltage Slope
dVOUT/dt(off) Turn-off Voltage Slope
RL=26 from VOUT=11.7V to VOUT=1.3V
V/s
LOGIC INPUT (Per each channel)
Symbol VIL IIL VIH IIH VI(hyst) VICL
(**) Per island
Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage
Test Conditions VIN = 1.25V VIN = 3.25V IIN = 1mA IIN = -1mA
Min 1 3.25
Typ
Max 1.25
10 0.5 6 6.8 -0.7 8
Unit V A V A V V V
4/20
1
VNQ810M
VCC - OUTPUT DIODE
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=0.5A; Tj=150C Min Typ Max 0.6 Unit V
ELECTRICAL CHARACTERISTICS (continued) STATUS PIN (Per each channel)
Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT= 1.6 mA Status Leakage Current Normal Operation; VSTAT= 5V Status Pin Input Normal Operation; VSTAT= 5V Capacitance ISTAT=1mA Status Clamp Voltage ISTAT=-1mA Min Typ Max 0.5 10 100 6 6.8 -0.7 8 Unit V A pF V V
PROTECTIONS (Per each channel)
Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Current limitation Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 15 20 0.7 5.5V < VCC < 36V IOUT=0.5A 0.9 1.4 1.4 VCC-41 VCC-48 VCC-55 Max 200 Unit C C C s A A V
Tj>TTSD
OPENLOAD DETECTION (per each channel)
Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A VIN=0V 1.5 2.5 Min 20 Typ 40 Max 80 200 3.5 1000 Unit mA s V s
OPENLOAD STATUS TIMING (with external pull-up) VOUT > VOL VINn IOUT < IOL
OVERTEMP STATUS TIMING Tj > TTSD VINn
VSTATn
VSTATn tSDL tDOL(off) tDOL(on) tSDL
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VNQ810M
Switching time Waveforms
vOUTn 90% 80%
dVOUT/dt(on)
dVOUT/dt(off)
10% t VINn
td(on)
td(off)
t
TRUTH TABLE
CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L
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VNQ810M
ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
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VNQ810M
Figure 1: Waveforms
NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VCC INPUTn OUTPUT VOLTAGEn STATUSn undefined VUSD VUSDhyst
OVERVOLTAGE VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn OUTPUT VOLTAGEn STATUSn VOUT>VOL VOL VCCVOL
OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj INPUTn OUTPUT CURRENTn STATUSn TTSD TR
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1
VNQ810M
APPLICATION SCHEMATIC
+5V +5V +5V VCC1,2 Rprot STATUS1 VCC3,4
Rprot
INPUT1 Dld
Rprot
STATUS2
OUTPUT1
Rprot
C
INPUT2
Rprot
STATUS3
OUTPUT2
Rprot
OUTPUT3 INPUT3
Rprot
STATUS4 OUTPUT4 INPUT4 GND1,2 GND3,4
Rprot
RGND +5V +5V VGND DGND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / 2(IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2.
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VNQ810M
Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
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VNQ810M
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RLOpen Load detection in off state
V batt.
VPU
VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2)
GROUND
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VNQ810M
Off State Output Current
IL(off1) (uA)
1.6 1.44 1.28 1.12 0.96 0.8 0.64 0.48 0.32 0.16 0 -50 -25 0 25 50 75 100 125 150 175
High Level Input Current
Iih (uA)
5
Off state Vcc=36V Vin=Vout=0V
4.5
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Clamp Voltage
Vicl (V)
8 7.8
Status Leakage Current
Ilstat (uA)
0.05
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 0 -50 -25 0 25 50 75 100 125 150 175 0.01 0.02 0.03 0.04
Vstat=5V
Tc (C)
Tc (C)
Status Low Output Voltage
Vstat (V)
0.8 0.7
Status Clamp Voltage
Vscl (V)
8 7.8
Istat=1.6mA
0.6
Istat=1mA
7.6 7.4
0.5 0.4 0.3 0.2
7.2 7 6.8 6.6 6.4
0.1 0 -50 -25 0 25 50 75 100 125 150 175
6.2 6 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNQ810M
On State Resistance Vs Tcase
Ron (mOhm)
400 350 300 250 200 150 100 100 50 0 -50 -25 0 25 50 75 100 125 150 175
On State Resistance Vs VCC
Ron (mOhm)
300 275
Iout=1A Vcc=8V; 13V & 36V
250
Tc= 150C
225 200
Iout=1A
175 150
Tc= 25C
125
Tc= - 40C
75 50 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
Openload On State Detection Threshold
Iol (mA)
60 55 50 45 40 35 30 25
Input High Level
Vih (V)
3.6 3.4
Vcc=13V Vin=5V
3.2 3 2.8 2.6 2.4
20 15 10 -50 -25 0 25 50 75 100 125 150 175 2.2 2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Low Level
Vil (V)
2.6 2.4 2.2
Input Hysteresis Voltage
Vhyst (V)
1.5 1.4 1.3 1.2
2 1.8 1.6 1.4
1.1 1 0.9 0.8 0.7
1.2 1 -50 -25 0 25 50 75 100 125 150 175
0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNQ810M
Overvoltage Shutdown
Vov (V)
50 48 46 44 42 40 38 36 34 32 30 -50 -25 0 25 50 75 100 125 150 175
Openload Off State Voltage Detection Threshold
Vol (V)
5 4.5
Vin=0V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Turn-on Voltage Slope
dVout/dt(on) (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
500 450
Vcc=13V Rl=13Ohm
Rl=26Ohm
400 350 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
ILIM Vs Tcase
Ilim (A)
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Vcc=13V
Tc (C)
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VNQ810M
Maximum turn off current versus load inductance
ILM AX (A) 10
A
1
B C
0.1 1 10 L(mH)
A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V Values are generated with RL=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
100
1000
t
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VNQ810M
SO-28 DOUBLE ISLAND THERMAL DATA
SO-28 Double island PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.5cm2, 3cm2, 6cm2).
Thermal calculation according to the PCB heatsink area
Chip 1 ON OFF ON ON Chip 2 OFF ON ON ON Tjchip1 RthA x Pdchip1 + Tamb RthC x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb (RthA x Pdchip1) + RthC x Pdchip2 + Tamb Tjchip2 Note RthC x Pdchip1 + Tamb RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1Pdchip2
RthA = Thermal resistance Junction to Ambient with one chip ON RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2 RthC = Mutual thermal resistance
Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_am b (C/W) 70 60 50
RthA
40 30 20 10 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7
RthB
RthC
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VNQ810M
SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(C/W)
100
0,5 cm ^2/is land 3 cm ^2/is land 6 cm ^2/is land
10
One channel ON
1
Two channels ON on same chip
0.1
0.01 0.0001
0.001
0.01
0.1 time(s)
1
10
100
1000
Thermal fitting model of a four channels HSD in SO-28
Tj_1
C1 C2 C3 C4 C5 C6
Pulse calculation formula
Z TH = R TH + Z THtp ( 1 - )
where
= tp T
0.5 0.35 1.8 4.5 11 15 30 0.0001 7.00E-04 6.00E-03 0.2 1.5 5 150 6
R1 Pd1
R2
R3
R4
R5
R6
Thermal Parameter
Area/island (cm2) R1=R7=R13=R15 (C/W) R2=R8=R14=R16 (C/W) R3=R9 (C/W) R4=R10 (C/W) R5=R11 (C/W) R6=R12 (C/W) C1=C7=C13=C15 (W.s/C) C2=C8=C14=C16 (W.s/C) C3=C9 (W.s/C) C4=C10 (W.s/C) C5=C11 (W.s/C) C6=C12 (W.s/C) R17=R18 (C/W)
Tj_2
Pd2
C13
C14
R13
R14
R17
R18
Tj_3
Pd3
C7
C8
C9
C10
C11
C12
R7
R8
R9
R10
R11
R12
13
Tj_4
Pd4
C15
C16
R15
R16
T_amb
8
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VNQ810M
SO-28 MECHANICAL DATA
DIM. A a1 b b1 C c1 D E e e3 F L S 7.40 0.40 17.7 10.00 1.27 16.51 7.60 1.27 8 (max.) 0.291 0.016 18.1 10.65 0.10 0.35 0.23 0.50 45 (typ.) 0.697 0.393 0.050 0.650 0.299 0.050 0.713 0.419 mm. MIN. TYP MAX. 2.65 0.30 0.49 0.32 0.004 0.013 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.012
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VNQ810M
SO-28 TUBE SHIPMENT (no suffix) Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
All dimensions are in mm.
A
C B
28 700 532 3.5 13.8 0.6
TAPE AND REEL SHIPMENT (suffix "13TR") REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 12 1.5 1.5 7.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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VNQ810M
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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